This paper was originally presented at the IEE Colloquium on "Electromagnetic Hazards to Active Electronic Components", 14th January 1994, IEE Colloquium Digest no 1994/008.

Response of 74XX logic circuits to ESD transients

Tim Williams, Elmac Services

  1. Introduction
  2. Outline of Experiment
  3. Results
  4. Discussion
  5. Conclusions and acknowledgements
  6. References

1. Introduction

The susceptibility of digital equipment to external transients is of considerable importance in design, both to ensure a reliable instrument, and to ensure that the instrument will meet contractual and legal EMC requirements. A major problem with digital products is susceptibility to single event upset, typically caused by an external electrostatic discharge (ESD). Often, the form such an upset takes is an invalid change of state of a latched device, somewhere within the circuit, which corrupts the circuit operation.

Most of the EMC design principles that have evolved over the last couple of decades [1] have concentrated on minimizing the interference amplitude that is present at a susceptible circuit node, such as a logic input, by focussing attention on the coupling path to that node. While this is a valid and necessary approach, attention can also be given to minimizing the inherent susceptibility of a given node. This paper reports the results of observations made on the susceptibility to a local ESD event of different samples of a specific device.

2. Outline of Experiment

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A single-sided PCB carrying a simple logic circuit was constructed; the circuit and layout are shown in Figure 1 and Figure 2. The susceptible nodes are the clock inputs of a dual D-type flip-flop, of the generic type 74XX74. One input is driven via 10cm of track adjacent (1mm) to its ground return, the other via 10cm of track 12.5mm from its ground return. The driving device in each case is one unit of a standard logic inverter, to represent a typical circuit source impedance. The inputs to the inverter can be tied low or high via a switch, thus setting the clock inputs high or low respectively. The D inputs are tied permanently high, and the Q outputs drive an LED each, so that the state of each Q output is visible. The Q outputs are both cleared regardless of the state of the clock input via a pushbutton switch driving the Reset inputs. The circuit is battery operated to avoid any external connections. The devices are standard 14-pin DIL packages, socketed to allow different types to be interchanged.

The purpose of the circuit was to show, via the LEDs, when the latches changed state from L to H as a result of a spurious signal on the clock input(s) latching in the H on their D inputs. Since the circuit itself is quiescent, changes would only be due to external interference coupling into the clock input node with respect to its ground return path. Once the latch changes state, this is indicated on the LED until the device is manually reset.

This interference was generated for the purposes of the experiment by an ESD simulator, applied to the local chassis. Figure 3 shows the experimental setup. The simulator was a KeyTek MZ15 with a contact discharge tip to IEC801-2:1991. Applying the simulator in contact mode to a fixed point as shown, although not exactly representing IEC801-2 test conditions, resulted in a highly repeatable experiment that yet approximated to the kind of coupling that would be experienced in a practical circuit. The exact waveform appearing at the susceptible nodes was not measurable with available instrumentation. However the purpose of the experiment was to determine relative susceptibilities of different configurations of the same circuit, rather than to try and compute an absolute susceptibility.

3. Results

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Tests were carried out to determine the threshold level of applied ESD voltage which just caused each latch to trip. In general FF1 (the larger susceptible loop area) tripped at a different threshold to FF2, with the smaller area. The repeatability of this experiment, provided that care was taken to retain physical layout, was found to be better than 20V (the MZ15 display resolution is 10V). The variables were:

The first checks were made on a MM74HC74AN device as the D-type, driven by a MM74HC14N inverter. Then, various samples of devices of the same type and from the same batch, and of different types (logic families), were tested. These gave the thresholds as listed for mean and standard deviation in Table 1 through to Table 4.

Table 1: 5 x MM74HC74AN
FF1: large loop area FF2: small loop area
Applied polarity +-+-
Clock low 0.81kV, sd 0.044-0.91kV, sd 0.037 1.31kV, sd 0.098-1.46kV, sd 0.075
Clock high 6.61kV, sd 0.55-6.35kV, sd 0.51 5.9kV, sd 0.5-6.6kV, sd 0.45

Table 2: 2 x SN74LS74AN
FF1: large loop area FF2: small loop area
Applied polarity +-+-
Clock low 1.04kV, sd 0.035-0.87kV, sd 0.02 1.04kV, sd 0.035-0.87kV, sd 0.02
Clock high 0.93kV, sd 0.035-1.06kV, sd 0.035 0.81kV, sd 0.035-0.65kV, sd 0.005

Table 3: 2 x 74F74N
FF1: large loop area FF2: small loop area
Applied polarity +-+-
Clock low 0.25kV, sd 0-0.2kV, sd 0 0.42kV, sd 0.015-0.47kV, sd 0.015
Clock high 4.63kV, sd 0.27-0.33kV, sd 0.02 3.59kV, sd 0-0.36kV, sd 0.025

Table 4: 2 x CD74AC74E
FF1: large loop area FF2: small loop area
Applied polarity +-+-
Clock low 1.30kV, sd 0.015-0.83kV, sd 0.005 1.36kV, sd 0.02-1.125kV, sd 0.035

Finally, an attempt was made to quantify the effect of the driver output impedance on the node sensitivity. With the D-type maintained as a MM74HC74AN selected for approximately average sensitivity, 5 different 74HC14 drivers (from two different manufacturers) and two 40106B devices were tested, with the clock maintained low. The results are shown in Table 5.

Table 5: Different drivers
FF1: large loop area FF2: small loop area
Applied polarity +-+-
74HC14 0.774kV, sd 0.016-0.88kV, sd 0.015 1.306kV, sd 0.04-1.46kV, sd 0.04
40106B 0.92kV, sd 0.005-0.67kV, sd 0.005 1.485kV, sd 0.015-1.14kV, sd 0.005

4. Discussion

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Effect of applied polarity

In general the threshold differences between positive and negative applied ESD pulses were of the order of 10-20%. This tends to confirm the expected waveshape of the transient at the affected node, where the initial unidirectional pulse is converted by circuit resonances [2] to a damped sinusoid, whose second peak of opposite polarity to the first will also be somewhat lower in amplitude. Notable exceptions are the 74F74 device, which with the clock held high was highly immune to positive pulses only; and both the 74AC74 D-type, and the 40106B driver, showed rather greater variations between polarities.

Effect of quiescent clock input state

Perhaps the most interesting finding was the remarkable improvement in immunity (7-fold) of the 74HC74 devices when the clock input was held high rather than low, as shown in Table 1. This improvement was not noted for the bipolar logic families, with the exception of the 74F74 for positive applied pulses. It is difficult to explain this effect, except that it may be connected with the fact that the clock input is active on the positive-going (low-to-high) transition. Since the choice of quiescent input level is to some extent in the hands of the circuit designer, it may be suggested that a considerable improvement in overall circuit immunity could be had by maintaining logic high levels at the inputs of CMOS D-types.

Susceptible loop area

H-fields induced by the ESD event will couple greater interfering voltages into a node with a large return loop area than into one with a small area. By contrast, E-field coupling will mostly be unaffected by loop area. The results show that for the HCMOS devices, immunity is improved by the smaller area, though not in direct proportion to the reduction in area, showing that a mixture of H- and E-field coupling is operating. For the other devices the effect is less marked, and indeed for the 74LS74A immunity is actually slightly worsened by the smaller loop.

Variations between devices

The low standard deviation values in all the tables show that susceptibility does not vary greatly between devices of the same type, manufacturer and batch number. Other experience [3] suggests that different manufacturers' parts of the same type can and do vary quite substantially in susceptibility.

Variations between logic families

The noticeably worst device was the 74F74. Even the apparently high threshold for positive applied pulses at clock high was anomalous, in that it was quite variable and would on occasion reset rather than set the flip-flop. The best overall family would appear to be HCMOS, although the LS and AC families appeared to have better immunity when the loop area was large and the quiescent input state was low. This equivocal result is in line with the variable RF susceptibilities of the different technologies reported in [4].

Comparison of different drive impedances

The standard deviation values in Table 5 show that, as with variations between flip-flops, variations between driving devices of the same family are insignificant. Changing from HCMOS to 4000B-series CMOS with its higher output impedance does change the susceptibility to some extent, but the changes are roughly evenly split between an improvement for positive applied pulses and a degradation for negative ones.

5. Conclusions

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Selection of logic family and circuit configuration can play a part in affecting the overall system immunity to ESD transients. This paper has evaluated the susceptibilities of different logic devices of the same type, and will hopefully offer some pointers to designing-in improved immunity in the future.

6. Acknowledgements

The author gratefully acknowledges the help of Comtest Ltd in the loan of the ESD test equipment. The circuit described is used as a demonstration in courses on immunity testing given by the author at ERA Technology Ltd.

7. References

  1. EMC for Product Designers, T Williams, Butterworth Heinemann 1992
  2. Designing for Electrostatic Discharge Immunity, D M Staggs, 8th Symposium on EMC, Zurich, March 1989
  3. Electromagnetic Susceptibility of Digital LSI Circuits Mounted on a Printed Circuit Board, M Klingler, M Szelag, M Heddebaut, 10th Symposium on EMC, Zurich, 9-11 March 1993
  4. RF Upset Susceptibilities of CMOS and Low Power Schottky D-Type Flip-Flops, D J Kenneally, D S Koellen, S Epshtein, IEEE National Symposium on EMC, Denver, May 23-25 1989
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