This paper was originally presented at the ERA conference "EMC 92 - Designing EMC into your product", 12th-13th February 1992, ERA Report 92-0011.
Available from Publication Sales, ERA Technology Ltd, Cleeve Road, Leatherhead, Surrey, KT22 7SA, UK. ERA is an independent international contract research, development and testing organisation, specialising in electrotechnology and related fields.
Many authors [1]-[6] have shown that printed circuit layout is a critical factor in the EMC performance of an electronic product containing digital circuits. The usual recommendation is that a ground plane layer in a multi-layer pcb construction is essential when clock frequencies exceed 30MHz, or with logic circuits that have transition times of less than 4ns, such as 74AC, 74F, 74AS or 74S families. Using simplifying assumptions it is possible to calculate radiated emissions from pcb traces and show that under extreme conditions of clock frequency and transition time, even a ground plane is insufficient to meet commercial radiated emissions limits [7].
The purpose of the ground plane is to provide a local return path for each and every signal track such that the loop area enclosed by the total circuit (signal plus return) is minimized. This results in minimum radiated emissions and low susceptibility to radiated noise, which are proportional to the area of the radiating or receiving current loop, and also in minimum induced ground noise voltage which is proportional to the inductance of the ground path. Note that the ground plane is not intended to act as a shield to the circuit traces.
Multi-layer construction is accepted practice for high performance circuits which use high value components such as 32-bit microprocessors and other VLSI peripherals. It may also be necessary to permit sufficiently high interconnect and component density, or to allow close control of track characteristic impedance. In these cases the much higher cost of multi-layer compared to conventional construction is either a small fraction of the overall product cost or is regarded as a necessary expense to meet the performance requirements.
But there are many more applications which use low or medium performance microprocessors and logic, such as single chip or 8-bit devices with clock frequencies between 4 and 12MHz, and subsidiary logic families of the 74HC or 74LS variety. The component cost must be low, no more than a few tens of pounds, and every means must be sought to keep the overall unit cost as low as possible. For these applications multi-layer pcb construction is too expensive and double-sided plated through hole is the most sophisticated pcb technology that can be used.
Fortunately the reduced clock frequencies and slower transition times make the EMC design easier. Good layout practice within the parameters of the double sided board construction can contribute to acceptably low emissions and high immunity and in many cases will allow further measures, such as a screened enclosure, to be dispensed with. Ott [1],[2] and others have covered the necessary practices, such as ensuring local returns for clock signals between ICs, and proper positioning of decoupling capacitors to minimize track distance between the points to be decoupled. Yet these practices are not yet widespread among designers of medium performance digital circuits. Note: in 1997, they are becoming more so!
A good example of the difference that can be made by a change in ground routing is offered by the layout of Figure 1, which is based on an actual case study. It concerns a 68HC11 single chip microprocessor whose E clock output at 2MHz was feeding a 74HC00 gate for timing purposes. Another output of the 74HC00 was fed back to a port input on the microprocessor. The two chips were positioned close together so that the signal tracks were relatively short (about 5cm). Unfortunately their 0V returns were connected to opposite ends of a long ground trace, so that the 2MHz squarewave return currents flowed around a loop that was virtually the entire area of the board! The overall system of which this circuit was a part was exceeding the EN55022 "B" limits for conducted emissions. Making a simple link from point A to point B (one extra short track) reduced the emissions of 2MHz harmonics in the 18 - 30MHz region by up to 15dB. Further links between other sections of the 0V return, to create an ad-hoc ground grid layout, gave an extra few dB improvement.
It seems that many designers do not appreciate quantitatively how much better a double sided construction with a correctly designed ground plane can be, compared with a board which is not laid out with its EMC performance in mind at all (but see note above). A practical demonstration of the difference is worth much more than theoretical guidelines, and this paper reports the results of a circuit which has been built to provide such a demonstration.
This is a small circuit containing a few logic ICs, which has been built up to two very different pcb layouts. The electrical functions and components used in the two layouts are absolutely identical.
The circuit itself consists of a 40MHz TTL-level crystal oscillator package driving a pseudo-random binary sequence (PRBS) noise generator, and a comb generator (Figure 2). The PRBS has a selectable cycle frequency of 1.2 or 19.5kHz, while the comb generator can produce harmonic spacings of 2.5, 5 or 10MHz. 74HC logic circuits are used throughout. The outputs of each of these generators can be enabled or muted and are fed via a 74HC244 buffer to a collection of interface connectors at one end of the board. Each unit is powered by a 5V battery pack mounted on the board and is therefore entirely self-contained if no cables are connected to the interfaces.
The two layouts are shown in Figure 3 and Figure 4. Both layouts are carried on standard 100 x 160mm Eurocard size boards. Layout 1 is designed to the best achievable practice. One side of the board is dedicated to a ground plane while the other carries the signal and +VCC tracks. The components are closely spaced and laid out to minimize the length of tracks which carry the higher frequency signals. Narrow tracks allow routing between IC pads to optimize this. Decoupling capacitors are located close to the devices' +VCC pins and connect straight to the ground plane. The +VCC rail is carried on a wide track which offers a reasonably high distributed capacitance to the ground plane.
By contrast, Layout 2 is very poorly designed. Devices are spread out further so that track distances are longer. No ground plane is used, and no attempt is made to route ground return paths near to critical signal tracks. Most damaging is that both the 0V and +VCC tracks are routed quite haphazardly and result in large loops carrying high di/dt currents; the output buffer is returned to the 0V input via a long track, and its decoupling capacitor is returned to its 0V pin via a track which takes in all the output connectors and is about 6" long.
These features are unhappily common in many designs which have been left to a CAD auto-routing package with no instructions as to proper high frequency layout rules.
Figure 5 and Figure 6 compare the radiated emissions of these two layouts, measured from 30 to 300MHz with horizontal polarization at a distance of 1m. In both cases the comb generator was enabled at 10MHz harmonic spacing. No cables were connected; the boards were run entirely on their own.
Layout 1 shows almost no emissions above the noise level (those which are visible on the plot are mostly Band II ambients). Layout 2, on the other hand, shows strong levels of 10MHz harmonics. The third harmonic of the 40MHz signal, which is distributed from the clock oscillator to other ICs around the board, is 25dB above the noise; other harmonics of the 10MHz comb are 10 - 20dB above those produced by layout 1. This comparison demonstrates the improvement of at least 10 - 25dB in differential mode radiated emissions alone, due only to circulating currents on the board, that is obtainable simply by adopting good layout practice. Later note: common mode emissions are also produced by the board alone, i.e. from common mode currents on the tracks; these also contribute to the total board-only emissions.
Differential mode (and common mode) radiation from the board alone is only one source of interference coupling. A more potent source is the common mode current that flows on connected cables [8] . Figure 7 and Figure 8 show the radiated emissions that are measured when a 1m length of screened cable is connected via the D-type connector on each board.
In this case the emissions are primarily due to ground noise voltage which is coupled onto the screen of the cable at the connector. The board layout determines the noise voltage that is present at this point. The two traces of Figure 7 and Figure 8 demonstrate again the 10 - 25dB improvement that is obtained by using a ground plane and a well designed layout.
These plots also show another characteristic of cable radiation. A 1m length is a quarter wavelength at 75MHz. Given that the far end of the cable is open circuited, the input impedance of the antenna formed by the cable falls to a minimum at multiples of a quarter wavelength and hence the maximum common mode current flows at this frequency. Thus the greatest radiating efficiency should occur around 75MHz, and the plots show this - in fact the peak emissions occur around 80 - 85MHz, which suggests that the electrical length of the cable is slightly shorter than 1m due to parasitic loading effects. Comparing Figure 5 with Figure 7 shows that some harmonics are enhanced by 30dB by cable coupling, and other harmonics enhanced to a lesser extent. Keeping ground noise voltages off cable sheaths is vital and is critically dependent on the induced ground noise at the cable connection point with reference to the rest of the circuit. Layout 2 couples the cable sheath to a point which carries a high noise current since it is between the 0V pin of the buffer IC and its decoupling capacitor. Layout 1 connects the sheath directly to the ground plane, at a point at which little noise current is flowing.
This paper has concentrated on the improvements in emissions that are achievable by the proper layout of digital circuits. Similar improvements can also be obtained in immunity to RF fields [9] . The difference between a particularly good layout and a particularly bad one can exceed 20dB. These improvements are obtained without the expense of a multi-layer board construction and in fact the unit cost added to achieve them is usually nil; at most a change from single sided to double sided construction is necessary. All that is required is an awareness on the part of the layout designer of which factors contribute most to the board's EMC performance, and a willingness to take these factors into account at the beginning of the layout design. The demonstration circuit described here is a tool to help instil that awareness.
Elmac Services